232 Layer NAND - Howard Marks VMware Explore 2022
Transcript
>> Welcome to VMware Explore 2022, with the CTO Advisor Studio. Come on in and consume some content. >> All right, this is the last video for VMware Explore 2022. Keith Townsend, your host. The CTO Advisor Studios. It has been an amazing show. We've talked everything from CXL with Stephen Foskett. We had the Grey Beards on Storage. We've talked to Chris Wolf, Amanda Blevins, the Americas CTO. We've had the technical and strategic conversations. Now this is more of a passion project for me.
We're about to have one of my mentors from when he was hardcore unemployable. Now he's, you know, he's given up and now- >> Now I'm employed. >> Now he's just employed. >> Nobody understands it. Not even me. >> It's been a couple years now. He works for VAST Data but we're not talking about VAST Data directly. We're hijacking the show you gave to Ray, Grey Beards on Storage. This is the unofficial Grey Beards on Storage. >> This is the other Grey Beards on Storage.
>> This is the other Grey Beards on Storage. I have with me, Howard Marks, not that Howard Marks. Howard Marks, deepstorage on Twitter. How's it going, Howard? >> It's going great. >> So Howard, Micron announced this super nerdy thing a while back ago, they kind of scooped the industry with 232-Layer NAND. >> Yep. >> And they made an absolute big deal of it. Matter of fact, I'm headed there next week to shoot some content with them, they're really excited about it.
You know, I'm a cloud, I'm cloudy enterprise architect-y thing. And I need people like you to tell me why 232-Layer NAND is important. >> Because stacking is how we make flash cheaper. So back in the day, 19, in the nineties, the flash that was in an SSD had like a 49 nanometer diameter per cell. >> That's huge. >> And it got denser by shrinking the diameter. >> Right. >> And so we got down to about 12 nanometers. >> Okay.
>> But at about 12 nanometers there's only a handful of electrons in that cell. And the leakage that gets created when you erase starts to get so large, you can't error correct it anymore. So you can't get smaller than that. >> So let's talk about the layer of that manufacturing process, versus the layer- The manufacturing process for CPUs. 12 nanometers for a CPU would be considered fat today, >> Right. >> 12, 14 nanometers. Intel had a hard time going from 14 nanometers to 10, but the nature of a CPU and the nature of storing, >> So, so when we use, when we use those nanometer terms, >> Right.
>> for anything but flash, we're talking about the size of the smallest thing that they can apply via lithography to the cell. >> And we, we're talking about zeros and ones. >> No, no, no. We're talking about the little copper wires that connect the transistors together. >> Gotcha. >> So when you say seven nanometers, the little copper wire that connects the the transistors together is seven nanometers wide. >> Okay. >> The transistor is about three times that big.
Flash cells have to be even bigger than that. So for a given node of lithography, the size of the cell in flash is still a multiple of that. >> Gotcha. >> So we're talking about dimensions of different things. >> Okay. >> But the point there was just, we had plainer flash, which is how DRAM and CPUs are made, where there's one transistor built up and then they're connected like a circuit board. >> Right. >> But when we got to the point where you couldn't make the cell smaller, because it wouldn't get, be reliable as a charge trap anymore, we had to go find some other way to get more bits per square millimeter of silicon.
>> Gotcha. >> And being a New Yorker, I understand completely, when you run out of land, you build up. And that's what the flash vendors did. So Samsung was the first. They found a way to build up to 16 layers and layer and semiconductor means different things. In this case layer means a whole cell. In the manufacturing process that's made up of about 20 layers of resists to get applied and lithographed and such. But for this conversation, a layer is a bit.
>> Okay. >> And the problem with stacking is the manufacturing process builds up layers of the various materials. >> Literally, as you're talking, I'm thinking about 3D printing. >> It, it's actually, you drop a little bit of a liquid on the wafer and it spins to get it completely even. >> Okay. Gotcha. >> And then it gets exposed to light that causes some of that to stick. And then it gets washed and the part that didn't, that didn't stick gets washed off and rinse repeats like 10 times to make a cell.
>> That sounds labor intensive. >> All automated. All sealed. >> Right. But even with the machinery needed to do that repeatedly consistently across millions, >> The lithography machines are made by two vendors in the world, Zius and a Dutch company, ADML. >> Okay. >> If you want to order a lithography machine for seven nanometer, that machine costs several hundred million dollars and has a two year lead time. >> Okay. >> But most of the cost of a chip is the start, the wafer, getting it into the factory.
The additional going, well, instead of doing this wash, apply, spin, light, repeat 10 times, we do it a hundred times. You've only raised the cost a couple of percents. >> Okay. >> So building high costs a little bit more than not building high, but most of the cost is in having the wafer. So it's cheaper to build high. >> Gotcha. I never, I never knew this stuff. >> The problem is you do all of this apply, wash, release.
Then you have to etch little tiny holes, perfectly straight, through all those layers of silicon and silicon dioxide that you've laid down. And then you have to plate the inside of that hole with copper or gold to make it conductive. And the flash foundries keep learning, how to get that little tiny hole perfectly straight, longer and longer, so they can stack higher and higher. >> Okay. I really do get the skyscape, scraper reference. Start out with a four story building.
Going from a four story building to a hundred story building >> It's actually very much Empire State building. 'Cause each cell layer is a little bit shorter. It's a staircase. Because that way you there's an opening to create a connection into each one. >> Okay. >> And so how deep the stacks are keeps getting higher and higher. So when Micron says they have 232 layers, they're actually taking advantage of the next piece of technology, which is, I can't make a stack this high and drill those holes that accurately all that way.
So they're making stacks on top of each other. So they make a stack and they drill all the holes and they make all the connections in some layer of poly silicon. And then they put a insulating layer in and they start the whole thing and build another stack. So that 232 is actually 251 stacks. >> Okay. >> And that gets around the, you can only drill holes so straight, largely etch holes so straight. And as you know, over the next few years, I expect we'll see, you know, we'll go from 232, that's two stacks.
Couple of weeks after Micron made that announcement Solid IM announced like 224, so that, everybody's playing leap frog. This generation is there. The next generation may be about 300, and then we'll get to, well, instead of two stacks, it's four stacks. We'll go, so we'll go from like 300 to like 400. 'Cause the first time we do four stacks, they won't be as high. Then we'll work our way up. But it's just the stacking is just how they make flash cheaper nowadays.
>> So they make flash cheaper. I understand the wafer. The wafer, most of the cost is in the wafer. We build up. Building up is much cheaper than either improving the density of the wafer at a single layer. >> Well, we couldn't improve the density anymore. >> We've reached the technical >> We hit the technical limit. >> So >> Because if you're going to do QLC flash, that needs 16 voltage levels. >> So we become, >> If you only have 16 electrons and one of 'em gets out, that changed the value.
>> So I'm following so far. Now what I'm not clear on, is what does that translate from a packaging perspective? Am I getting the same sizes? When I, as a consumer of flash, am I getting the same size packages, just cheaper? Or am I getting larger packages? >> So, they're still selling a one gigabyte, one gigabit, chip. And then eight of those chips go in the package you see if you open an SSD. But the chips are a little bit smaller.
So they get more of 'em on a wafer. So they're cheaper to make. >> Okay. >> When the density gets to where that physical, the two gigabit chip will fit in that physical package, they'll switch to two gig. >> So the PCB, they haven't gotten to the point where a two gigabit chip will play onto the same PCB yet. >> It's not the PCB, but when you look at a circuit board, the thing you say is a chip, that package?
Actually holds multiple chips. >> Gotcha. >> And when the physical, the millimeter by millimeter size of that chip, at two gigabits fits in that size package with that many legs, which is an industry standard, they'll switch from doing one gigabit to two gigabit. 5 doesn't make any sense. >> Exactly. So essentially at that point, at the two gigabit point, that's when we get you know from, one terabyte to two terabyte, from four terabyte to eight, eight to sixteen. >> Right.
>> Learned a lot. That's a lot. So let's, bonus question. I've talked to Steven about CXL. >> Yep. >> What does CXL play in all of this, if at all? >> So, so CXL is basically a mechanism for accessing memory over PCIe. >> Right. >> And what's really attractive about that, is it- It gets us past the limits of the number of memory channels the CPU can provide. So we can have a bigger memory space. >> Exactly.
>> But the exciting part is since we have PCIe switches and we can use PCIe as a network, we can have shared memory spaces. And so somebody could make a box with four terabytes of DRAM in it and eight PCIe ports that eight servers can use and all share that memory. >> Right >> That's really exciting, But it's memory is memory. >> Right. >> And flash memory is, well, we call it bit addressable but it's really 64-byte addressable chunks. 'Cause the CPUs read and write 64 bytes at a time >> We put a controller in front of that- >> A word line.
But flash is block oriented, like storage, and as flash gets denser, the blocks get bigger. So on today's QLC flash, the minimum right size to not, that for the chip is 64k. >> How much? >> 64k bytes. >> Okay. >> So >> That's rather large. When you're talking about bit addressable memory. That's like, super inefficient. >> And so if you put a controller on it, like the SSD guys do so that you do a 4k write and it writes 4k to the 64k page and wastes the rest, that's okay for an SSD.
'Cause the time it takes for the SSD to garbage collect and fix the waste, doesn't really matter. But if you're trying to treat it as memory and a guy writes 64 bytes, and it takes 64k bytes to hold it, that's going to get weird. So you need, kind of DRAM buffering to let your coalesce writes, and a management plane and member just trying to do that. But yeah, my, I'm excited about CXL, but I remain unconvinced about its expansion beyond the HPC world.
'Cause in the HPC world, guys will go, holy crap, I could have 20 terabytes of memory on, shared between eight servers? Great. Let me go write code. >> And they, they have that level of skill to do that. >> That's what they do. >> Yeah. >> When you get to the corporate world, I think even something like MemVerge, which is a kit to write like, a database engine, is too far down and we need a database engine that does an in-memory database that takes advantage of you know, something like Aerospike, that fully takes advantage of CXL.
>> So. >> 'Cause that would be, and you talk to it via sequel and the corporate guys know how to talk to it via sequel. And that would be much faster to get into a corporate data center. >> So, we've been doing this series The Future of the Data Center with Micron, and I've painted the markitecture picture of this. This is the unsponsored content, where we talk about that deep level of technical hurdles, what still needs to be done. While I'm still excited about that picture that I've drawn, this is like the stumbling blocks.
This is the stuff that needs to be figured out. Go back and watch the CXL video that I did with Steven Foskett that talks about the challenges around security, write access control. All these things that need to be figured out. And what Howard just said, which is, delivering the value at a high enough abstraction level where it makes sense for the average corporate data center and not just HPC which is the promise that I'm telling you that the industry is driving towards.
We'll see where we land. Maybe there'll be something in between, that the cloud providers take advantage of and not the private data center. We'll see. com. Thanks, VAST Data for loaning me Howard during the busiest part of the show, the last day, to talk about CXL 200 layer plus NAND. Talk to you next year. No, not next year. We'll talk to you at QCon in just a few weeks. Until then see you on Twitter.
